Engineering practice and selection experience from the Duyuan Electronics R&D team: covering high-speed interface design, radar and communications signal processing, heterogeneous computing platforms and China-based replacement, helping you avoid detours in device selection and solution delivery.
FPGA dev boards never have enough I/O: you need a high-speed ADC, an optical module, or LVDS sensors — and you don't want to redesign the PCB every time. FMC (FPGA Mezzanine Card, VITA 57 standard) solves this: one carrier board + a library of standard mezzanine cards, swap the card to change the interface. This article walks through LPC vs HPC, pin budget, and common mezzanine configurations.
Stitching four 1080p camera feeds into one 4K output looks like "just putting four pictures together," but behind it lies a bandwidth ledger: input bandwidth, DDR frame-buffer bandwidth, scaling engine bandwidth, and output bandwidth — four layers stacked on top of each other. Get the math wrong and you get stuttering, tearing, or DDR overload. This article walks through every layer from pixel clock upward.
Domestic substitution is not as simple as "swapping one chip." Many teams only compare unit price and logic resources during selection, only to discover once migration begins that toolchain, IP cores, PCB layouts, and engineer learning curves all need to be recalculated. This article gives you a TCO (Total Cost of Ownership) framework that itemizes every cost of migration, so you can decide whether it is worth doing.
The PCIe bandwidth bill is far more complex than the number on the datasheet—raw bandwidth, coding overhead, protocol overhead, DMA efficiency, and the DDR bottleneck each eat into that "16 GB/s". This article works through Gen3 x4/x8/x16, all the way to DDR and DMA matching, and gives a reusable method for estimating net bandwidth.
Along a production-line defect inspection pipeline, from camera pixels to the rejection signal, where exactly is the FPGA irreplaceable? This article first tallies the bandwidth budget of the full data flow, then breaks down the four roles FPGA plays in the vision pipeline, compares the real-time limits of traditional algorithms versus deep learning, and finally gives a deployable hardware selection through a real PCB solder-joint AOI station case.
Oscilloscopes, digitizers, phased-array radars, software-defined radios and high-speed vibration monitoring — the core of all these systems is "high-speed ADC sampling → data packing → transfer to the host for processing." Why must this step use an FPGA rather than an MCU, a DSP or a CPU sampling directly? Why have the FMC HPC connector and the PCIe x8 interface become the golden combination for high-speed acquisition cards? This article starts from a real 250MSPS acquisition project.
One of the most frequent questions Duyuan Electronics receives over the past two years is: "We used to use Xilinx XC7K325T, and now we need a China-based replacement. Can the Fudan Micro JFM7K325T be dropped in directly? How much code do we need to change? Do we need to redesign the PCB? How much performance do we lose?" This article puts three mainstream model pairs from the Fudan Micro JFM7 series and the AMD/Xilinx 7-series side by side, and explains exactly to what extent a "drop-in replacement" really holds.
It is 2026. AMD's newest Versal AI Edge has been on sale for years, and UltraScale+ is already a process node from a decade ago. Yet a significant share of the inquiries Duyuan Electronics receives every week still explicitly specify Kintex-7 (XC7K325T, XC7K410T, XC7K160T). Not because these customers cannot afford UltraScale+, but because in many real products Kintex-7 is actually the more rational choice. This article walks through four typical scenarios.
Over the past three years, domestic substitution in the FPGA industry has gone from a slogan to real orders. This article gives a 2026 horizontal comparison of mid-range Chinese FPGAs from Pango, FMSH and Anlogic.
The essence of quantitative trading is completing the information loop of market data arrival, signal computation and order transmission in the shortest possible time. This article uses the AMD Virtex UltraScale+ XCVU13P (VU13P) platform as the main thread, explaining why it fits quantitative trading and how to deploy it into a deliverable low-latency trading chain.
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