FPGA Clock Tree and Jitter Budget: Why Your High-speed Link Keeps Failing
PCIe drops occasionally, JESD204B won’t lock, video link flickers — often it’s not the RTL code, it’s the clock design. FPGA high-speed transceivers are extremely sensitive to reference clock jitter, and every stage of the clock tree from oscillator → clock buffer → FPGA global network adds jitter. This article explains how to calculate jitter budget, design the clock tree, and avoid common pitfalls.
1. Why High-speed Links Fear Jitter
FPGA high-speed transceivers (GTP/GTH/GTY) use embedded clock recovery (CDR), but the recovered clock quality depends on the reference clock. Excessive reference clock jitter causes:
- PCIe BER degradation: reference clock RMS jitter > 1 ps, Gen3 BER can worsen from 1e-12 to 1e-8.
- JESD204B sync failure: excessive SYSREF jitter, LMFC cannot align, link simply won’t lock.
- Video link flicker: pixel clock jitter shifts sampling points, causing jitter or horizontal bands.
- DDR timing margin loss: clock jitter eats setup/hold margin, memory errors at high temperature.
Key formula: jitter is additive — every stage of the clock tree adds jitter; total jitter is the RSS (square root of sum of squares), not simple sum.
2. How to Calculate Jitter Budget
Take PCIe Gen3 x8 as example: reference clock RMS jitter must be ≤ 1 ps (12 kHz ~ 20 MHz integration). Stage-by-stage calculation:
| Clock Tree Stage | Jitter (RMS) | Notes |
|---|---|---|
| Crystal oscillator (XO) | 0.3 ps | Low phase noise OCXO, 100 MHz |
| Clock buffer | 0.5 ps | Si5341 or 8T49N series |
| PCB trace + vias | 0.2 ps | Microstrip 5 cm, continuous impedance |
| FPGA global clock network | 0.3 ps | MRCC → BUFG → SERDES |
| Total jitter (RSS) | √(0.3²+0.5²+0.2²+0.3²) ≈ 0.67 ps | Below 1 ps spec, 33% margin |
What if Budget Is Exceeded
If total jitter calculates to 1.2 ps, exceeding PCIe Gen3’s 1 ps requirement, optimize in priority order:
1. Switch to lower-jitter oscillator: ordinary TCXO 1 ps → OCXO down to 0.3 ps, immediate improvement.
2. Better clock buffer: remove redundant buffers, use dedicated clock IC (Si5341 vs GPIO buffer).
3. Shorten PCB trace: oscillator close to FPGA, trace ≤ 5 cm, avoid vias.
4. Proper power decoupling: LDO supplies clock IC separately, not shared with digital circuits.
3. FPGA Clock Tree Structure
The FPGA internal clock tree is not a single line but multi-stage buffering:
| Stage | Resource | Purpose | Jitter Added |
|---|---|---|---|
| 1. External input | Clock pin (MRCC/SRCC) | Oscillator / external clock input | — |
| 2. MMCM/PLL | Mixed-mode clock manager | Multiply, divide, phase adjust | ≈ 0.1~0.3 ps |
| 3. Global buffer | BUFG / BUFGCE | Drive entire FPGA logic array | ≈ 0.1 ps |
| 4. Regional clock | BUFH / BUFR | Local clock domain, low jitter | ≈ 0.05 ps |
| 5. SERDES clock | CPLL / QPLL | High-speed transceiver reference clock | ≈ 0.2 ps |
Key Rules
- High-speed transceiver clocks must use dedicated pins: GTH/GTY reference clock pins are fixed, cannot use ordinary IO.
- Don’t cascade too many MMCM/PLL stages: two cascaded PLLs add jitter; one stage is better than two.
- Cross clock domains with FIFO: don’t cross domains in logic; metastability causes random errors.
- SDR/ADC clock must be同源 with data clock: JESD204B needs Device Clock and SYSREF同源 and synchronized.
4. Three Common Clock Pitfalls
Pitfall 1: Oscillator Too Close to Switching Power Supply
DC-DC ripple (mV level) modulates oscillator output, worsening jitter by 2~3×. Fix: keep oscillator away from DC-DC, use LDO for separate supply, add ferrite bead.
Pitfall 2: JESD204B SYSREF Not Aligned
SYSREF aligns LMFC (local multi-frame clock). If SYSREF and Device Clock are not同源, or trace skew too large, link randomly loses lock. Fix: SYSREF and Device Clock output from same clock IC, trace length matched.
Pitfall 3: Using Ordinary IO as SERDES Reference Clock
FPGA high-speed transceivers have dedicated reference clock pins (e.g., MGTREFCLK0P/N). If you connect oscillator to ordinary IO, you can multiply clock for logic, but SERDES CDR won’t lock — jitter includes global clock network noise.
Half of FPGA high-speed link reliability comes from logic design, half from clock design. Calculate jitter budget correctly, build the clock tree properly, and do power decoupling well — many “intermittent link drops” disappear. Clock is not magic; it’s an engineering problem you can calculate.
