China FPGA Chips: From a Universal Chip to Independent Breakthrough — How Far Have We Come, What Still Lacks

A market ruled for three decades by the AMD (Xilinx) and Altera duopoly is now being rewritten in China. With the market approaching RMB 40 billion and self-sufficiency expected to break through 30%, high-end devices above 500K gates remain a forbidden zone for domestic players — this article dissects the progress, fundamentals and deep waters of China FPGA.

FPGA (Field-Programmable Gate Array) is often called the “universal chip”: it has no fixed function — after being “programmed” with a hardware description language, it can become a dedicated circuit, and can be redefined within milliseconds. Protocol processing at gigabit-per-second rates in base stations, beamforming in radar, low-latency matching in financial trading, deterministic acceleration in AI inference — scenarios that demand high throughput, low latency and the ability to change on demand are the home turf of FPGA. It is the third widely validated general-purpose computing form after CPU and GPU, and the last fortress-level category on China’s “chip shortage” list to be conquered.

Unlike most chip categories, the difficulty of FPGA is twofold: it requires building an extremely complex chip, and writing the software toolchain that makes the chip “obedient”. In other words, FPGA vendors do not sell a chip; they sell a complete ecosystem of “hardware + software + IP + ecosystem”. This is why the market has been dominated by two companies for three decades, and why domestic substitution has been so difficult — and so critical — here.

I. Thirty Years of Duopoly: Why FPGA Is So Hard

The global FPGA market has long been a stable duopoly: AMD (which completed its roughly $49 billion acquisition of Xilinx in February 2022) and Intel’s Altera (acquired by Intel for $16.7 billion in 2015; 51% of its equity was sold to Silver Lake in September 2025 to operate as an independent company) together hold 80%–85% of high-density FPGA revenue; Xilinx alone accounts for about 51% of the market. The low-power edge market is led by Lattice, and the radiation-hardened aerospace market belongs to Microchip.[1][2][3]

This landscape has a three-layered moat. The first is patents and architecture: nearly all core FPGA patents are held by American companies — from look-up table (LUT) structure and programmable interconnect to configuration circuits — accumulated over decades into a tight barrier that later entrants can hardly bypass at the architecture level. The second is the software toolchain: Xilinx’s Vivado and Intel’s Quartus are the “operating systems” developers rely on; timing closure, place-and-route, debugging and IP generation all happen on top of them. The third is engineer habits and ecosystem: a equipment vendor’s communication protocol stacks and signal-processing algorithms have been accumulated on Vivado for over a decade, with code assets and debugging experience layering up — switching platforms means starting over. This switching cost is harder to surmount than any process barrier on the wafer.[3][7]

That is why the pursuit of China FPGA has never been as simple as “making a chip” — it is a protracted battle around architecture, EDA and ecosystem.

II. The Turning Point: Seven Years After the ZTE Incident

In April 2018, the U.S. Department of Commerce issued a seven-year export denial order against ZTE, prohibiting American companies from selling components, software and technology to it. The incident directly caused ZTE to lose RMB 6.983 billion that year, and made “FPGA supply cutoff” a real fear across the industry for the first time — at the time, high-end FPGAs in communication base stations had almost no domestic alternative, and base-station baseband FPGAs and server chips from Broadcom, Intel and others were explicitly marked by brokerages as “currently no substitute available”.[4][5]

Since then, with the ZTE incident as the trigger, domestic substitution was elevated to a national strategic level: the Big Fund kept increasing investment, the Xinchuang (IT application innovation) policy expanded, and the Entity List added repeated pressure. Downstream customers shifted from “dare not use domestic” to “must prepare domestic”. China FPGA vendors thus obtained the two scarcest things — order entry points and trial-and-error opportunities. In the industry’s words, substitution advances along a “rural areas encircling the cities” path: military-special and low-end consumer markets completed substitution first; communication and industrial mid-range followed; high-capacity devices above 500K gates are still under attack.

The Three-Stage Leap of Substitution

Breakthrough period (2018–2020): from “unusable” to “daring to try”

Big Fund investment began, Xinchuang pilot projects started; industries sensitive to supply-chain security — military, power, rail transit — took the lead in adopting domestic devices, and China FPGA went from zero to one.

Volume ramp (2021–2023): mid- and low-end scaled substitution

40/55nm processes matured and 28nm products entered mass production in succession; mid-range markets such as communication, industrial control and machine vision ramped up, and domestic vendors opened up in scenarios such as server smart NICs and industrial control systems.

Hard-core attack (2024–2026): charging toward high-end and ecosystem

FinFET process products landed, billion-gate devices were released, heterogeneous SoPC moved toward commercial use; the main battlefield shifted to frontal attack on high-capacity devices, advanced processes and the software ecosystem.

III. Where We Stand Today: Market, Share and Self-Sufficiency

First, the totals. According to a forecast by China Research Intelligence (中研普华), China’s FPGA chip market was about RMB 24.99 billion in 2024, up 19.78% year on year, expected to exceed RMB 33.22 billion in 2025, with a compound annual growth rate of about 22.5% from 2025 to 2030. Frost & Sullivan’s figures differ slightly: the China FPGA market grew from about RMB 15.03 billion in 2020 to about RMB 33.22 billion in 2025, a compound growth of about 17.2%; it also forecasts the global FPGA market will exceed $12.5 billion in 2025. Markets and Markets expects the global market to reach about $19.34 billion by 2030, with a 2025–2030 CAGR of 10.5%, and Asia-Pacific as the fastest-growing region globally.[6][8][9][10]

Then the results. Over the seven years of domestic substitution, the most intuitive change is in share: the two international giants’ combined share in China fell from about 78% in 2021 to about 57% in 2025, while Ziguang Tongchuang, Fudan Microelectronics and Anlogic together approached 29%. Morgan Stanley expects China’s FPGA self-sufficiency rate to rise to about 37% by 2025, with local vendors’ overall TAM growing from $476 million in 2021 to about $2 billion, a compound growth of about 42% over the period.[9][11]

But breaking it down, the quality of substitution is uneven: military-special and low-end consumer markets have basically achieved autonomy; communication and industrial mid-range are accelerating penetration; high-capacity devices above 500K gates remain “a forbidden zone for international vendors” — domestic flagship products concentrate below 500K logic elements, with non-advanced processes holding the main share.[6][11] Beyond scale growth, the structural hard battles are just beginning.

IV. The Vendor Landscape: Five Forces Advancing in Parallel

China FPGA is not a one-player show, but a multi-polar landscape with Ziguang Tongchuang as the leader, Fudan Microelectronics and Anlogic as the two wings, and Gowin and Jingwei Qili specializing in niche tracks, plus Chengdu SinoMicro, Zhongke Yihaiwei and others as special/military-industrial forces.

Table 1: Major China FPGA vendors and product ladders (compiled from public sources, 2026)

Manufacturer	Representative products & technology	Process node	Primary markets
Ziguang Tongchuang (PANGOMICRO)	Logos-2 (25K–200K LUTs); Titan-3 (FinFET, targeting international high-end); PG3T1300/1500 billion-gate; Kosmo-2/3 (CPU+FPGA+NPU heterogeneous)	28nm / FinFET	Communication, cybersecurity, data center, AI inference, industrial, automotive
Fudan Microelectronics	28nm billion-gate (China’s first mass-produced, ~700K logic elements, 13.1Gbps SerDes, DDR4, hard ARM core + AI acceleration); four series: 10M/100M/billion-gate/SoPC	28nm in mass production, 14nm trial	Communication core networks, medical devices, automotive, special
Anlogic	28nm PH1A series, FPSoC (SoC FPGA); ELF5 low-power small-capacity (2.5K–15K LUTs, 55nm)	28nm / 55nm	Industrial control, display drivers, AI server peripherals, consumer electronics
Gowin	Gowin LittleBee GW1N (55nm), ChenXi GW2A low-power series	55nm / 28nm	Low-power edge, industrial, consumer
Jingwei Qili	CPE reconfigurable computing platform (processor + programmable logic fusion)	28nm level	Industrial, edge intelligence, China-based Xinchuang

Two signals are worth noting. First, Ziguang Tongchuang launched the FinFET-based Titan-3 series in 2024; the PG3T1300 and PG3T1500 are called by the company “China’s only two billion-gate high-end FPGA products with independent IP” and have entered high-end communication and data center scenarios; in 2025 it completed IPO tutoring filing, a landmark step for China FPGA toward the capital market.[12][13] Second, Fudan Microelectronics, a veteran that started FPGA R&D in 2004, was the first to achieve mass production of a 28nm billion-gate chip — “China’s first” — and extended downward into 10-billion-gate trial production and the PSoC product line.[14][15] Anlogic, meanwhile, follows a “fully self-developed + dual-track high and low end” route: 28nm mid-range + 55nm low-power small-capacity, with the ELF5 series released in 2026 targeting AI server peripherals and industrial automation.[16]

V. Technology Progress: From 55nm to FinFET, From Millions of Gates to Billions

Looking at the cross-section of process and scale, China FPGA is completing a generational leap: 40/55nm devices have long been mature in mass production, 28nm has become the current mainstream node, FinFET process products landed in 2024, and 14nm-level products are entering trial production. In logic scale, domestic devices have crossed from millions of gates to tens of millions and gained a foothold; the billion-gate level (roughly 700K–1M logic elements) achieved the “zero to one” breakthrough.[14][15][17]

Mature nodes (55/40nm) · mass-produced

Low-power small-capacity devices (Gowin LittleBee, Anlogic ELF, etc.) cover industrial control and consumer electronics; domestic players already have complete competitiveness in this range.

Current mainstream node (28nm) · fully deployed

Ziguang Tongchuang Logos-2/Titan-2, Fudan’s billion-gate, and Anlogic PH1A are all based on 28nm; high-speed interfaces such as SerDes (10–13.1Gbps), DDR3/DDR4 and PCIe Gen3 are gradually complete.

Advanced node (14nm / FinFET) · breaking the ice

Ziguang Tongchuang Titan-3 (FinFET, 2024) targets international high-end; Fudan’s 14nm 10-billion-gate enters trial production, with high-end capacity and power metrics converging toward international products.

Architecture leap (heterogeneous integration) · advancing in parallel

Domestic SoPC/PSoC is moving from “FPGA + hard-core CPU” to “CPU + FPGA + NPU” multi-core heterogeneous (Ziguang Kosmo, Fudan PSoC), with the route toward Xilinx Zynq/Versal beginning to take shape.

But we must stay sober: process is only the entry ticket; architecture and software are the real dividing line. International giants’ high-end products (AMD Versal ACAP, Intel Agilex 7) have upgraded FPGA into “adaptive computing platforms”, integrating AI Engine vector processor arrays, multi-domain dedicated architectures and data-center-grade network IP — the Versal AI Core series claims a 2.7x performance-per-watt ratio over 10nm competitors. Full benchmarking of such platform-level capability is still in early pursuit for domestic players.[3][18]

VI. The Real Deep Water: Five Major Challenges

Challenge 1: EDA and the Software Toolchain — the Hardest Wall

Professor Wei Shaojun, director of the Institute of Microelectronics at Tsinghua University, once said bluntly that domestically, on “logic synthesis” and “place-and-route” — the two cores of EDA — “there is basically no contribution, and they are not even touched”. That remark remains the most painful footnote of China FPGA. When Chengdu SinoMicro released its first billion-gate logic-synthesis-hardened EDA tool in 2026, its head likewise pointed out that for large-scale FPGAs, “hardware performance breakthrough is one thing, but the more critical performance bottleneck lies in the software”.[19][20]

The gap is tangible in the development experience: on designs targeting 200MHz+, domestic PDS/TD tools often need 3–4 rounds of place-and-route iteration, even manual floorplanning, to converge, while Vivado may pass in one pass; the IP catalog depth is also visibly shallow — domestic toolchains cover about 40 cores such as DDR3/DDR4, PCIe Gen2/3, SGMII and basic video interfaces, while JESD204B/C and other high-speed ADC/DAC IPs commonly used remain blank.[21][22] Every iteration of the toolchain directly determines the usability of China FPGA in high-end designs.

Challenge 2: Ecosystem and Engineer Habits — a Moat Harder to Cross Than Process

As discussed above, the code assets, debug scripts and engineer muscle memory accumulated on Vivado/Quartus over more than a decade constitute the strongest user stickiness. Switching FPGA platforms for an equipment vendor means rewriting protocol stacks, re-timing, re-buying IP — an extremely high cost. To break this “habit barrier”, domestic vendors cannot rely on device price-performance alone; they need migration tools, compatible IP and close technical support — a long-term ecosystem project.[3][7]

Challenge 3: Process and High-End Device Capability

Domestic flagship products still concentrate at mature nodes of 28nm and below; 7nm-and-below advanced processes, ultra-large-scale logic resources and data-center-grade AI FPGA lag the international leaders; high-end device requirements such as ultra-high-speed SerDes (56G/112G PAM4), HBM integration and advanced packaging (2.5D/3D) are still being built. Constrained by external equipment and capacity, access to advanced processes is also less smooth than for international vendors.[8][23]

Challenge 4: Closing the Commercial Loop — From “Able to Make” to “Able to Sell Well”

Jingwei Qili CEO Wang Haili summarized six barriers China FPGA faces in reaching the market: chip price, system migration, software efficiency, product stability, after-sales maintenance and volume shipping. FPGA has a high usage threshold and long verification cycles; customers will not lower their requirements for stability and long-term supply just because of the “China-made” label. And domestic vendors’ revenue scale remains small, with R&D investment and capacity ramp-up pressures coexisting.[24]

Challenge 5: Talent Gap

FPGA is the chip category that most requires cross-disciplinary capability — device architecture, EDA algorithms and application development are all indispensable. At home, senior talents in EDA place-and-route algorithms are “almost nonexistent”, and senior engineers with both FPGA and system-level design experience have long been in short supply; talent reserves directly constrain the sprint toward high-end.[7][19]

VII. Breakthrough Directions: Four Visible Paths

Challenges are many, but the breakthrough paths are already clear — and being validated by the industry:

First, upgrade to “system solutions” instead of selling chips alone. China FPGA’s price-performance and service-response advantages in the mid- and low-end are obvious, but single-chip value is limited. Forming a complete “chip–board–system” chain with board vendors, solution providers and system integrators (as commonly seen in the “FPGA + board” bundling model in base stations and server NICs) to thicken the value is a realistic path to scale up domestic device shipments.[25]

Second, stake out deterministic computing in the AI era. AI inference and accelerator cards have rekindled FPGA’s value: low latency, reconfigurability and controllable power — especially suited to SmartNIC, edge inference and high-frequency trading. Data-center-grade AI FPGA is the new battleground of international giants, and also an opportunity window for domestic vendors to bypass direct GPU competition and enter through “compute offload + network processing”.[3][26]

Third, EDA attack shifts from “following” to “binding to devices”. The way out for domestic EDA is not to replicate Vivado, but to bind deeply with domestic devices, go deep and thorough in specific domains (special, industrial, video), build reputation with “good enough, stable, close service”, then gradually extend toward general-purpose high-end.

Fourth, capitalization and consolidation accelerate industry concentration. Ziguang Tongchuang is sprinting toward IPO, Anlogic is already listed, and many vendors have received Big Fund and industrial capital backing — listing financing will support advanced-process R&D and ecosystem investment, and industry consolidation will avoid scattered resources and form true head forces.[13][27]

Conclusion: From “Replacement” to “Definition”

In seven years, China FPGA completed the leap from “no chip available” to “dare to use domestic chips”: self-sufficiency approaching 40%, billion-gate devices in mass production, FinFET process landing, and five vendors standing firm in their tracks. But the deep water is equally real — EDA toolchains, high-end devices and the developer ecosystem still lag the international giants, and the commercial loop has just begun.

FPGA’s special nature is that it tests not a single-point breakthrough, but the systemic capability of “chip + software + ecosystem + scenarios”. Fortunately, China has the world’s largest downstream application market, the most complete board and system ecosystem, and wave after wave of substitution demand forced out by being “choked”. From “replacement” to “definition”, the path is long, but the direction is already irreversible.

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References (compiled from public sources, 2026)

• [1] AMD completes ~$49 billion acquisition of Xilinx (February 2022): AMD official press release / public reports
• [2] Intel sells 51% of Altera to Silver Lake (closed September 2025): AI Wiki industry event compilation
• [3] Global FPGA landscape (AMD ≈51%, two giants 80–85% of high-density revenue; Lattice low-power, Microchip radiation-hardened): SemiconductorX / Research Intelo
• [4] 2018 ZTE incident and RMB 6.983 billion loss: Eastmoney Xinchuang industry report / Xinhua, People’s Daily and other public reports
• [5] 2018 “no substitute for base-station FPGA”: The Paper citing CITIC Securities
• [6] China FPGA market size (RMB 24.99 billion in 2024, RMB 33.22 billion expected in 2025, 22.5% CAGR 2025–2030): China Research Intelligence (reported by Securities Times / CSN 2025-06)
• [7] “Three bottlenecks of patents/EDA/ecosystem”, “EDA algorithm talent gap”: Electronic Engineering Album “40 Years of FPGA”, Ziguang Tongchuang EDA column citing Wei Shaojun
• [8] Frost & Sullivan figures (China 2020 RMB 15.03 billion → 2025 RMB 33.22 billion, CAGR 17.2%; global over $12.5 billion in 2025): Electronic Engineering Album / 36Kr
• [9] Morgan Stanley: China FPGA self-sufficiency ~37% in 2025, local TAM $476M → $2B, CAGR ~42%: Gelonghui
• [10] Markets and Markets: global ~$19.34 billion by 2030, CAGR 10.5%: Anlogic 2025 annual report
• [11] In-China share (giants 78%→57%, three domestic vendors ≈29%; above 500K gates is an international forbidden zone): Securities Star 2026-09
• [12] Ziguang Tongchuang Titan-3 (FinFET), PG3T1300/1500 billion-gate, Kosmo heterogeneous: Ziguang Tongchuang official site / China Business Information Network
• [13] Ziguang Tongchuang completed IPO tutoring filing in 2025: China Business Information Network
• [14] Fudan’s 28nm billion-gate as China’s first mass production (~700K LC, 13.1Gbps SerDes, hard ARM + AI): 36Kr / Fudan Micro prospectus (via Electronic Engineering World)
• [15] Fudan four series (10M/100M/billion-gate/SoPC), 14nm trial: Sina Finance / CSDN industry compilation
• [16] Anlogic ELF5 (55nm, 2.5K–15K LUTs): Electronic Engineering Album 2026-05
• [17] China FPGA process and scale matrix (Ziguang 28nm, Fudan 28/14nm): CSDN industry compilation
• [18] Versal ACAP/AI Engine, 2.7x performance-per-watt: AMD official materials
• [19] “Basically no contribution to logic synthesis and place-and-route”: Ziguang Tongchuang citing Professor Wei Shaojun (2019)
• [20] “Large-scale FPGA bottleneck is in software”: Chengdu SinoMicro billion-gate EDA release (2026-06, Xin Shige)
• [21] Domestic EDA timing closure and IP catalog comparison: Shenzhen Informic toolchain review (2026-07)
• [22] Domestic EDA toolchain (PDS/TD) performance comparison: Electronic Engineering Album toolchain review
• [23] “Gap in 7nm-and-below advanced processes and data-center AI FPGA”: Sina Finance industry report
• [24] Jingwei Qili CEO Wang Haili on six market barriers: Jingwei Qili official site
• [25] “Chip-to-industry-solution capability needs improvement”: Sina Finance 2026-07
• [26] FPGA re-priced in AI/data center: Securities Star / FPGAInsights
• [27] Anlogic STAR Market listing and 2025 annual report: Shanghai Securities News

Duyuan Electronics · Industry Insights | Data as of September 2026; different institutions’ figures differ, each has been annotated with its source