TSN: How Deterministic Ethernet and Frame Preemption Actually Land on an FPGA

Standard Ethernet’s best-effort delivery is not enough for industrial control: a large file transfer on the same cable can delay a motion-control frame by milliseconds. TSN (Time-Sensitive Networking, IEEE 802.1) adds time synchronization, time-gated scheduling and frame preemption to turn Ethernet into a predictable, calculable network. This article breaks it down into numbers and shows how to land it on FPGA boards.

Why standard Ethernet is “unpredictable” in industrial control

Standard Ethernet is essentially “whoever arrives first sends first”. The problem is not average latency but the uncontrollable worst case:

• On a 1Gbps port, a 1518-byte large frame is being transmitted;
• At the same moment, a 64-byte high-priority motion-control frame arrives at the switch port;
• The switch cannot interrupt the frame in flight, so the control frame queues and waits.

This queuing wait is where jitter comes from. It does not matter in an office network, but in multi-axis motion control, robot joints and servo coordination the control cycle is typically 125µs or shorter; a control frame that arrives a few hundred microseconds late means the axes fall out of sync.

TSN does not change the cable. It overlays a set of deterministic scheduling rules on Ethernet so the worst case becomes designable and calculable.

What TSN actually solves: four standards together

TSN is not one protocol but a set of standards from the IEEE 802.1 working group. The four commonly used blocks:

Sub-standard	What it solves	Plain meaning
802.1AS (gPTP)	Network-wide time sync	All switches and nodes share one clock, within 1µs
802.1Qbv (TAS, time-aware shaper)	Traffic sent on a schedule	Each port’s queues have a “gate schedule”, deciding when real-time and normal traffic go out, to the microsecond
802.1Qbu / 802.3br (frame preemption)	High-priority frames not blocked by large frames	A long frame can be interrupted halfway, yield, then resume
802.1Qat / 802.1Qav	Bandwidth reservation and queue management	Reserve fixed bandwidth for real-time streams so normal traffic cannot burst into it

Think of TSN as a dedicated bus lane on the cable: first all intersections align their clocks (gPTP), then the bus must use the dedicated lane at scheduled times and other traffic runs off-peak (TAS), and a bus can slip through a gap when a truck blocks the road (preemption).

Three numbers: cutting latency from milliseconds to microseconds

How long a frame occupies a 1Gbps link

First the physical layer. 1Gbps is 10^9 bit per second; transmit time = bits / 10^9.

Frame type	Bytes	Bits	1Gbps transmit time
Minimum Ethernet frame	64 B	512 bit	0.512 µs
Normal frame	512 B	4096 bit	4.10 µs
Standard maximum frame	1518 B	12144 bit	12.14 µs
Jumbo frame	9000 B	72000 bit	72.0 µs

A standard maximum frame occupies the link for about 12.1µs. Without preemption, a high-priority control frame waits up to that full 12.1µs, plus switch forwarding and queuing — jitter can easily reach hundreds of microseconds to milliseconds.

How much blocking preemption removes

802.1Qbu/802.3br splits a long frame at a 64-byte boundary. When a high-priority frame arrives:

• If the in-flight long frame has passed the first 64 bytes (fragment checkpoint), interrupt it immediately;
• Send the high-priority frame fully (worst case 0.512µs);
• Record the breakpoint on the long frame and resume it later.

Compare worst-case blocking:

• No preemption: control frame waits for a whole large frame ≈ 12.14µs;
• With preemption: control frame waits for less than one fragment (≤64B, 0.512µs) plus its own transmit time.

This gap from ~12µs to ~1µs is why TSN can reach microsecond control cycles.

How gPTP time synchronization aligns

The TAS schedule must use one shared time across the network, or each switch opens its own gates at different times. 802.1AS (gPTP) aligns master and slave via link-layer timestamp exchange:

• The grandmaster sends periodic sync messages;
• Each switch hops hardware-timestamps the packet in/out to correct link asymmetry;
• End nodes adjust their local clock from the grandmaster.

In practice gPTP end-to-end offset is typically within ±1µs, which is the prerequisite for TAS schedules at microsecond granularity. Without good sync, all the scheduling is meaningless.

Landing TSN on an FPGA: from MAC to time gating

TSN timestamps and gating demand hardware precision; a CPU plus software stack cannot reach microseconds — that is where FPGA sits. A typical FPGA TSN node chain:

1. PHY: multi-rate 100M/1G/2.5G/5G, supporting frame preemption (802.3br) fragmentation and reassembly;

2. Ethernet MAC: hard or soft MAC, outputting timestamped streams;

3. TSN IP core: gPTP slave clock, TAS time-gated scheduler, preemption/reassembly in FPGA logic;

4. Business logic: motion-control frames, sensor data and normal traffic into separate queues.

The key point: timestamps must be stamped in hardware at the PHY/MAC boundary, not recorded by software after packet receipt — the latter alone costs tens of microseconds. FPGA keeps “packet arrives → timestamp → look up gate table → decide when to send” in one clock domain, which is its core advantage over a general CPU gateway.

Selection: three board tiers for TSN nodes

Different TSN scenarios demand different logic resources and transceiver counts; choose by budget and port count:

Board	FPGA platform	TSN role	Why
XCKU15P core board	Kintex UltraScale+	Multi-port TSN aggregation / edge gateway	Abundant logic, GTH transceivers and hard Tri-Mode MAC; runs gPTP slave + multi-way TAS scheduling + business acceleration together
DUF7690T	FudanMicro JFM7VX690T (pin-compatible with XC7VX690T)	High-reliability / domestic TSN node	Virtex-7 class, industrial temperature, for supply-chain and reliability-sensitive domestic lines
DUK7410T	FudanMicro JFM7K410T (pin-compatible with XC7K410T)	Single/dual-port TSN endpoint	Kintex-7 class, lower cost; enough for one gPTP slave port plus single TAS, suited to volume endpoints

A common mix: DUK7410T as field endpoints, DUF7690T as domestic work-cell gateways, XCKU15P as the multi-port TSN aggregation node for the whole line, so ordinary IP/video traffic and real-time control traffic are separated by TSN queues on one cable.

Case: merging one mixed cable onto TSN

A machine originally used two cables: one for PLC and servo real-time control, one for camera images and logs. After the retrofit they merged to one gigabit cable split by TSN:

• Real-time control frames use a dedicated TAS gate, 125µs cycle, about 10% bandwidth reserved;
• Camera bulk traffic uses the normal queue, and preemption guarantees it never blocks the control frame;
• gPTP aligns the 4 servo nodes within 1µs.

Measured after retrofit: worst-case control-frame jitter dropped from about 800µs to under 3µs, cables halved from two to one, and switch ports and wiring cost dropped together.

Determinism is not making the network faster, but turning the “worst case” from unknowable into calculable — that is exactly where FPGA puts time into hardware.

Further reading

• [10G/25G fiber backhaul: building long-range high-bandwidth links](/article/fiber-backhaul-10g-25g/)
• [FMC mezzanine ecosystem: extending boards with dedicated interfaces](/article/fmc-mezzanine-ecosystem/)
• [PCIe bandwidth planning: calculating bandwidth between host and board](/article/pcie-bandwidth-planning/)