MPSoC vs Pure FPGA vs MCU+ARM: How to Choose Among Three Heterogeneous Routes
The most common question in embedded selection is not “which chip is the fastest” but “should I use MPSoC, pure FPGA, or MCU+ARM with external logic?” These three routes have clear boundaries in compute allocation, development efficiency, cost, and power — this article turns the decision criteria into a calculable comparison table.
First, Clarify the Three Routes: They Solve Different Problems
| Route | Architecture | Good At | Bad At |
|---|---|---|---|
| MPSoC (Zynq series) | ARM Processing System (PS) + FPGA Programmable Logic (PL) on one chip | Hardware-software co-design: ARM runs Linux/control, PL does real-time parallel acceleration | Large-scale parallel logic like pure FPGA; ultra-low cost |
| Pure FPGA (Kintex/Virtex series) | Fully programmable logic, no built-in CPU | Hard real-time parallelism, high-speed interface direct connection, custom dataflow | Complex OS, protocol stacks, HMI |
| MCU+ARM + external FPGA/CPLD | MCU or ARM SoC runs main program, small external logic for glue | Cost-sensitive, control-dominant, minimal glue logic | High-bandwidth dataflow, multi-channel parallel acceleration |
Key judgment: if your system needs “OS + real-time parallel acceleration” on a single chip, MPSoC is the first choice; if the core value is all in parallel dataflow and high-speed interfaces, pure FPGA is more direct; if 90% of your system is control logic with only minor glue, MCU+external small logic saves the most.
First Ledger: How to Split Compute Requirements
The first step in selection is not looking at chips, but splitting your system’s compute needs into two categories: sequential control compute and parallel real-time compute.
Typical system compute breakdown:
| Task Type | Examples | Required Compute | Best Route |
|---|---|---|---|
| Linux/network protocol stack/filesystem | Device management, web UI, data logging | Dual-core ARM or above | MPSoC or MCU+ARM |
| Multi-channel parallel acquisition/processing | 8-channel simultaneous ADC, 4 video streams | FPGA logic (DSP/BRAM/LUT) | Pure FPGA or MPSoC PL |
| High-speed interface protocol | PCIe Gen3, 10G Ethernet, JESD204B | FPGA hard IP or logic | Pure FPGA or MPSoC |
| Simple state machine/IO expansion | Buttons, LEDs, UART/I2C bridge | Minimal LUT | MCU+CPLD/small FPGA |
| AI inference/neural networks | Object detection, classification, feature extraction | ARM NEON or FPGA acceleration | MPSoC (PL accel) or pure FPGA |
Rule of thumb: if sequential control tasks exceed 60% and need an OS, choose MPSoC; if parallel real-time tasks exceed 60% and are latency-sensitive, choose pure FPGA; if neither is significant, choose MCU+external small logic.
Second Ledger: Development Efficiency and Team Capability
The three routes differ significantly in development cycle and team skill requirements:
| Dimension | MPSoC | Pure FPGA | MCU+ARM+External Logic |
|---|---|---|---|
| Software development | C/C++ on Linux/bare-metal ARM | Almost no “software”, all RTL | C on MCU, minimal Verilog |
| Hardware development | Vivado for PL logic | All logic in Verilog/VHDL | MCU register config + glue logic |
| Boot time | PS boots Linux ~2–5 s | FPGA config done, <100 ms | MCU boot <10 ms |
| Team requirement | Both embedded C and FPGA RTL | Pure FPGA team | Standard embedded team |
| Debugging complexity | PS/PL interaction debugging complex | Timing closure is main challenge | Simplest |
If your team only knows embedded C and not FPGA, don’t force pure FPGA; if your team only knows FPGA and not Linux, the PS part of MPSoC becomes a bottleneck. MCU+ARM+external logic is the safe choice when team skills are limited.
Third Ledger: Cost, Power, and Board Area
| Dimension | MPSoC (ZU4EV class) | Pure FPGA (XCKU15P class) | MCU+External CPLD/small FPGA |
|---|---|---|---|
| Chip cost | Medium-high ($50–150) | High ($100–300) | Low ($5–20) |
| Board area | Single-chip integrated, small | Single chip but many peripherals | Two chips, larger |
| Typical power | 5–15 W | 10–25 W | 1–3 W |
| Peripheral devices | DDR, power management significant | DDR (if needed), high-speed transceivers | Minimal, no high-speed DDR |
| Production cost | Medium | High | Low |
Cost-sensitive consumer/industrial control products: MCU+external small logic remains the most economical route; MPSoC fits mid-to-high-end products needing hardware-software co-design on one chip; pure FPGA is for extreme parallel performance requirements where cost is not the primary concern (radar, communications, high-speed acquisition).
Decision Table: Five Questions to Determine Your Route
Combine the three ledgers into a decision table, answer in order:
| # | Question | If “Yes” | If “No” |
|---|---|---|---|
| 1 | Does the system need Linux/complex OS? | Lean MPSoC | Continue |
| 2 | Are there 4+ parallel data streams or high-speed interfaces (PCIe/10G/JESD)? | Lean pure FPGA or MPSoC PL | Continue |
| 3 | Does your team write FPGA RTL? | Can go MPSoC or pure FPGA | Go MCU+external logic |
| 4 | Must single-board BOM cost stay under $30? | Go MCU+external logic | Continue |
| 5 | Need both control and real-time acceleration on one chip? | MPSoC | Pure FPGA or split-board |
Typical combined answers: needs Linux + multi-channel parallel + team knows FPGA → MPSoC; no Linux + core all in parallel dataflow → pure FPGA; no Linux + only minor glue logic → MCU+external logic.
Common Misconceptions: When MPSoC Is the Wrong Choice
1. Only running control, no PL acceleration needed: using MPSoC wastes half the die area; use an ARM SoC (like i.MX series) + minimal logic instead.
2. PL logic exceeds MPSoC capacity: XCU4EV has ~154K LUT in PL; if your parallel processing needs 300K+ LUT, go to pure FPGA (XCKU15P ~372K LUT) or larger MPSoC (ZU7EV/ZU19EG).
3. Team doesn’t know FPGA at all: if the PL side sits empty, buy a cheaper Zynq-7000 or just use an ARM SoC.
4. Need ultra-short boot time: MPSoC PS booting Linux takes seconds; if your product must run within <100 ms of power-on, pure FPGA or MCU is more suitable.
Board Recommendations: What Hardware Fits Each Route
- MPSoC route → DUUZ4EV (XCZU4EV Zynq UltraScale+ MPSoC): ARM Cortex-A53 + R5F plus PL logic, suitable for mid-to-high-end projects needing hardware-software co-design (industrial gateways, video processing, edge AI).
- Pure FPGA route → DUKU15P (XCKU15P Kintex UltraScale+ core board): 372K LUT plus 32 GTH transceivers, suitable for large-scale parallel logic and high-speed interface-intensive projects (radar signal processing, high-speed acquisition).
- Domestic/low-cost route → PBC7Z021G (domestic Zynq SoC core board): domestic heterogeneous SoC compatible with XC7Z021, suitable for projects needing MPSoC architecture but with budget constraints or domestic substitution requirements.
Selection is not about choosing the strongest chip, but about choosing the architecture that best matches your system’s compute distribution. First split your tasks into sequential and parallel categories, calculate the proportion of each, then consider team capability and cost constraints — the boundaries between the three routes become clear.
Further Reading
- [FPGA Selection Decision Matrix: Aligning Resources, Transceivers, and Price](/article/fpgaselection-decision-matrix/)
- [Domestic ZYNQ (PBC7Z020G/021G) Replacement Practice: From Schematic to Software](/article/domestic-zynq-replacement-practice/)
- [Multi-Camera Onboard AI Inference: FPGA Pipeline from Sensor to NPU](/article/multi-camera-onboard-ai-inference/)
