The core of Software Defined Radio (SDR): digitize the RF signal as early as possible, and leave the signal processing to the FPGA. A typical wideband SDR frontend chain is: antenna → LNA → mixer → ADC → FPGA (DDC + FFT + demodulation). Along this chain, FPGA transceiver bandwidth, DDR buffering, and DSP horsepower determine how wide an instantaneous bandwidth you can achieve.
FPGA dev boards never have enough I/O: you need a high-speed ADC, an optical module, or LVDS sensors — and you don't want to redesign the PCB every time. FMC (FPGA Mezzanine Card, VITA 57 standard) solves this: one carrier board + a library of standard mezzanine cards, swap the card to change the interface. This article walks through LPC vs HPC, pin budget, and common mezzanine configurations.
Oscilloscopes, digitizers, phased-array radars, software-defined radios and high-speed vibration monitoring — the core of all these systems is "high-speed ADC sampling → data packing → transfer to the host for processing." Why must this step use an FPGA rather than an MCU, a DSP or a CPU sampling directly? Why have the FMC HPC connector and the PCIe x8 interface become the golden combination for high-speed acquisition cards? This article starts from a real 250MSPS acquisition project.
