PCIe drops occasionally, JESD204B won't lock, video link flickers — often it's not the RTL code, it's the clock design. FPGA high-speed transceivers are extremely sensitive to reference clock jitter, and every stage of the clock tree from oscillator → clock buffer → FPGA global network adds jitter. This article explains how to calculate jitter budget, design the clock tree, and avoid common pitfalls.
The PCIe bandwidth bill is far more complex than the number on the datasheet—raw bandwidth, coding overhead, protocol overhead, DMA efficiency, and the DDR bottleneck each eat into that "16 GB/s". This article works through Gen3 x4/x8/x16, all the way to DDR and DMA matching, and gives a reusable method for estimating net bandwidth.
Oscilloscopes, digitizers, phased-array radars, software-defined radios and high-speed vibration monitoring — the core of all these systems is "high-speed ADC sampling → data packing → transfer to the host for processing." Why must this step use an FPGA rather than an MCU, a DSP or a CPU sampling directly? Why have the FMC HPC connector and the PCIe x8 interface become the golden combination for high-speed acquisition cards? This article starts from a real 250MSPS acquisition project.
