FPGA Clock Tree and Jitter Budget: Why Your High-speed Link Keeps Failing
PCIe drops occasionally, JESD204B won't lock, video link flickers — often it's not the RTL code, it's the clock design. FPGA high-speed transceivers are extremely sensitive to reference clock jitter, and every stage of the clock tree from oscillator → clock buffer → FPGA global network adds jitter. This article explains how to calculate jitter budget, design the clock tree, and avoid common pitfalls.