Guide to High-End UAV Computing Architecture: FPGA vs MPSoC
Introduction
In high-end UAV onboard computing architecture design, "pure FPGA or MPSoC?" is a core question that cannot be avoided. Pure FPGA excels in hardware parallelism and deterministic latency; MPSoC integrates CPU, real-time cores and programmable logic on a single chip, balancing software flexibility with hardware acceleration. The two are not simply substitutes but correspond to fundamentally different workload characteristics.
As an FPGA-focused engineering team, Duyuan Electronics draws on field experience with both the ZU19EG and VU13P product lines to lay out the technical logic behind this selection and provide reference configurations across scenarios.
1. Understanding UAV Workload Heterogeneity
A UAV is a typical multi-task real-time system; onboard computing requirements fall into four broad categories.
Real-Time Flight Controlis the most fundamental layer. The IMU outputs data above 1 kHz; the flight controller must perform attitude estimation, EKF fusion, attitude and rate loop control, and update the ESC via PWM or DShot. The entire loop typically runs within 1 ms, and worst-case jitter must be tightly constrained.
AI Autonomous Computinghandles object recognition, visual obstacle avoidance, SLAM and path planning. These are compute-intensive but can typically tolerate tens of milliseconds of latency.
Payload Processingprocesses video, mapping and inspection data, prioritizing throughput over hard real-time performance.
Deterministic Signal Processingcovers radar pulse compression, electronic warfare signal processing, high-speed sensor interfaces and time synchronization. Their common trait is microsecond-level completion with extremely low timing jitter.
These four workloads impose vastly different requirements on chip architecture — the root of the selection question.
2. Pure FPGA: The Boundaries and Value of Determinism
2.1 When to Choose Pure FPGA
The core value of pure FPGA is determinism. Logic circuits run in hardware parallel; the signal path is fixed after synthesis and place-and-route, with no OS scheduling, interrupt latency or cache misses. FPGA can therefore achieve nanosecond-level, zero-jitter response.
In radar signal processing, matched filtering, pulse compression and FFT must complete within each pulse period; FPGA hardware pipelines guarantee output in a fixed number of clock cycles. Electronic warfare is the most representative high-end pure-FPGA scenario. Lockheed Martin, working with Altera, flight-demonstrated a Gen12 EW transceiver based on the Altera Agilex 9 Direct RF FPGA on a Group 2 UAV, detecting, identifying and geolocating real emitters in under 12 months while meeting size, weight and power constraints. Agilex 9 Direct RF supports direct RF sampling, eliminating the interface bottleneck between a separate RF front-end and digital processing.
Compact radar simulators also rely on FPGA. The 27th Institute of CETC designed a P-band radar target and jammer simulator using FPGA baseband processing, weighing under 6 kg and consuming under 130 W, generating noise, deceptive and dense false-target jamming. Such applications have highly fixed algorithms and extreme latency sensitivity, making pure FPGA almost a mandatory choice.
2.2 Engineering Platform for Pure FPGA
For radar signal processing and EW scenarios requiring extreme determinism, Duyuan Electronics built the VU13P PCIe board around the AMD Virtex UltraScale+ XCVU13P. The XCVU13P offers 1,728K logic cells, 3,456K registers and 12,288 DSP slices on TSMC 16nm FinFET+ process. Onboard 4GB DDR4 (2400 MT/s, 64-bit) delivers ~19.2 GB/s theoretical bandwidth. The PCIe Gen3 x16 edge connector provides ~15.75 GB/s one-way and ~31.5 GB/s bidirectional theoretical bandwidth.
The FMC+ connector provides 34 LA pairs plus 24 HA pairs of differential IO and 16 GTY transceiver pairs, directly interfacing high-speed ADC/DAC mezzanine cards via JESD204B for high-channel-count RF signal processing. The VU13P logic scale and high-speed interface density make it ideal for radar pulse compression, EW signal processing and multi-channel high-speed acquisition.
3. MPSoC: Heterogeneous Integration and Hardware/Software Co-Design
3.1 When to Choose MPSoC
The core idea of MPSoC is covering multiple task types with one chip. The AMD Zynq UltraScale+ MPSoC integrates a quad Cortex-A53 application processor, dual Cortex-R5 real-time processor, FPGA logic and DSP blocks, interconnected by a high-bandwidth AXI fabric.
The key advantage of this heterogeneous architecture is task isolation。Safety-critical real-time flight control runs on the Cortex-R5 with FreeRTOS or bare-metal code to guarantee deterministic control cycles; AI inference and complex algorithms run on the Cortex-A53 with Linux and its mature software ecosystem; FPGA logic handles sensor interfaces, data preprocessing and hardware acceleration. The three share on-chip memory and a high-speed bus, avoiding the“main-controller-plus-coprocessor”inter-chip bandwidth bottleneck and latency of traditional architectures.
A quantitative comparison: for 1080p@30fps real-time semantic segmentation combined with a PID control loop, the Zynq solution achieves 8ms end-to-end latency versus 22ms on the NVIDIA Jetson TX2. The key difference is the 32 GB/s AXI bandwidth between PS and PL, allowing sensor data to flow between CPU and FPGA with minimal overhead.
Zynq UltraScale+ MPSoC is already deployed in UAV flight control. Enclustra developed a UAV flight and video controller using a ZU-series MPSoC for position control and trajectory tracking, with dynamically configurable FPGA connections between sensors and actuators and a dual-redundant flight control unit. DJI's 2016 Inspire 2 used a Zynq XC7Z045 SoC in its CineCore 2.0 imaging system for 4K/60fps real-time video processing — an early landmark Zynq application in high-end UAVs.
3.2 Engineering Platform for MPSoC
For integrated mission computing, Duyuan Electronics built the ZU19EG development board around the Zynq UltraScale+ MPSoC XCZU19EG. The ZU19EG belongs to the Zynq UltraScale+ EG family and integrates a complete processing system with large programmable logic on one die. The PS includes a quad Cortex-A53 (up to 1.5 GHz), dual Cortex-R5, Mali-400 GPU, DDR4 controller, PCIe Gen3, USB 3.0 and GbE; the PL offers ~1,143K logic cells, 1,968 DSP slices, 70.6 Mb RAM and abundant GTH/GTY transceivers.
This“hardware-software co-design, compute and logic combined”heterogeneous architecture runs complex OSes like Linux on the PS while achieving nanosecond-level deterministic response and hardware-pipeline acceleration in the PL. The PS-PL AXI HP/ACP interface enables shared memory and direct register access to hardware accelerators without a PCIe protocol stack, with typical latency under 500ns. The ZU19EG draws ~30W total, far below a“FPGA board plus industrial PC”combo, giving it a clear edge in space- and thermally-constrained embedded environments.
4. Four Dimensions for Selection
First, the latency magnitude. If a task must complete in microseconds with zero jitter — radar pulse compression, EW signal processing, high-speed motor control — pure FPGA is the only option. If the window is milliseconds, MPSoC real-time cores plus FPGA acceleration are fully adequate.
Second, algorithm changeability. Where algorithms are fixed once deployed, pure FPGA hardening is appropriate. Where algorithms iterate rapidly and require fast validation — such as AI object detection model updates — MPSoC software flexibility wins.
Third, system integration requirements. For strict SWaP constraints, single-chip MPSoC significantly reduces board area and power. For multi-channel direct RF sampling or ultra-high-speed acquisition, pure FPGA with a separate RF front-end may be preferable.
Fourth, functional safety and certification. Aviation-grade UAVs must account for DO-254/DO-178C certification. The MPSoC heterogeneous architecture naturally supports task isolation, placing safety-critical functions on a dedicated real-time core to simplify certification compliance. Pure-FPGA functional safety design requires a more rigorous hardware verification process.
5. Recommended Models
MPSoC Direction
AMD Zynq UltraScale+ MPSoC (ZU Series) is the most mature MPSoC choice for UAVs. The ZU5EV and ZU7EV integrate quad A53, dual R5, Mali-400 GPU, H.264/H.265 codec and FPGA logic on one chip, suiting integrated mission compute platforms for high-end UAVs. The ZU19EG offers higher logic density and DSP resources for simultaneous flight control, AI inference and high-speed sensor interfaces. The ZU3EG suits power- and size-sensitive lightweight designs and has been used as an onboard computer for indoor-navigation UAVs.
AMD Versal AI Edge Gen 2（2VE3858/2VM3858） represents the next generation. It integrates an Arm Cortex-A78AE application processor, Cortex-R52 real-time processor, Mali-G78AE GPU, FPGA logic and AI inference accelerator (AIE-ML v2), delivering over 200k DMIPs and 2x AI inference performance. New Wave Design has launched the V3211 SOM based on this chip for UAVs, loitering munitions and wearable EW, with single-chip intelligence handling preprocessing, AI inference and post-processing on one die.
Microchip PolarFire SoC FPGA offers unique advantages in low power and determinism. Its deterministic architecture ensures real-time execution of critical tasks while delivering 6,500 CoreMarks at just ~3W — ideal for power-sensitive high-end UAVs. Integrated crypto acceleration and trusted hardware principles also suit scenarios with strict firmware-integrity and data-security requirements.
Pure FPGA Direction
Altera Agilex 9 Direct RF Series is the flagship choice for EW and radar. Devices like the AGRW039 support up to 64 Gsps direct RF sampling, integrating high-speed ADC/DAC and FPGA logic and eliminating a separate RF front-end. Lockheed Martin's SWIFT program has proven its operational capability on Group 2 UAVs.
AMD Virtex UltraScale+ VU13P/VU9P offers extreme logic density and high-speed interfaces. The VU13P features millions of logic cells, abundant DSP slices and high-speed GTY transceivers for radar pulse compression, EW signal processing and multi-channel high-speed acquisition. The FMC+ connector interfaces high-speed ADC/DAC mezzanine cards via JESD204B.
AMD Kintex UltraScale+ XQRKU060 represents radiation-hardened options with in-orbit infinite reconfiguration, suited for UAVs or near-space platforms in high-radiation environments.
6. Typical Configurations on Duyuan Electronics Platforms
Option 1: Integrated Mission Compute Platform (MPSoC-centric)
Centered on the ZU19EG board: the PS runs Linux + PX4/ROS 2, the Cortex-R5 runs safety-critical attitude control, and the PL handles sensor preprocessing and AI inference acceleration. Suitable for medium-to-large UAVs handling flight control, visual navigation and object recognition. Duyuan Electronics provides one-stop full-stack FPGA solutions — hardware design, logic development, IP customization and embedded software — accelerating the path from selection to prototyping.
Option 2: Dedicated Signal Processing Platform (Pure FPGA)
Centered on the VU13P board, high-speed ADC/DAC mezzanine cards connect via FMC+ to build radar or EW signal processing systems. The VU13P's 1,728K logic cells and 12,288 DSP slices readily support hardware pipelines for multi-channel pulse compression, FFT and matched filtering — suited for military or special-mission UAV tasks requiring extreme deterministic latency.
Option 3: Heterogeneous Co-Processing (MPSoC + discrete FPGA)
Using the ZU19EG as the main compute platform, a VU13P connects via PCIe Gen3 x16 or high-speed GTY links as a dedicated coprocessor. The ZU19EG handles flight control, mission management and system scheduling, while the VU13P performs real-time radar or EW front-end signal processing. This split balances software ecosystem with hardware determinism and is a common architecture for today's highest-end UAV compute platforms.
Conclusion
The answer to pure-FPGA-vs-MPSoC does not depend on which chip is inherently better, but on the tension between a workload determinism requirements and algorithm changeability. Pure FPGA is irreplaceable for microsecond-level determinism and dedicated signal processing; MPSoC wins on system integration, software flexibility and multi-task isolation. High-end UAV architecture design places each class of compute task on the hardware best suited to it: real-time flight control on the Cortex-R5, AI inference on the Cortex-A53 with FPGA acceleration, and radar signal processing in pure-FPGA hardware pipelines.
With the ZU19EG and VU13P product lines covering the full spectrum from MPSoC to pure FPGA, and one-stop full-stack FPGA solutions, Duyuan Electronics provides end-to-end support — from chip to system — for selecting, validating and deploying high-end UAV compute architectures.